Improvements in microprocessor designs have led to microprocessors with a high operating frequency. Current microprocessor designs have operating frequencies of 400 megahertz ("MHz") and higher. The increase in operating frequency, however, has not led to fully acceptable performance gains. One of the main components affecting performance gains is created by the microprocessor execution units idling during delays in external memory access. The delays in external memory access are caused by the conventional design characteristics of static random access memory ("SRAM") cells, read only memory ("ROM") cells, and dynamic random access memory ("DRAM") cells.
To counteract the performance losses associated with external memory access, Rambus Inc., of Mountain View, Calif., developed a high speed memory system. FIG. 1 illustrates the Rambus high speed memory system. In particular, system 100 shows a master device, memory controller ("MC") 10, coupled to memory devices DRAM 20, SRAM 30, and ROM 40. Each device is coupled in parallel to signal lines DATA BUS, ADDR BUS, CLOCK, V.sub.REF, GND, and VDD. DATA BUS and ADDR BUS show the data and address lines used by MC 10 to access data from the memory devices. CLOCK, V.sub.REF, GND, and VDD are the clock, voltage reference, ground, and power signals shared between the multiple devices. Data is transferred by a single device's bus drivers (not shown) driving signals on the bus. The signals are transmitted across the bus to a destination device (not shown). For one embodiment, system 100 is coupled to a central processing unit ("CPU") (not shown). Accordingly, MC 10 coordinates the data transfer between the memory devices of system 100 and the CPU.
To increase the speed of external memory accesses, system 100 supports large data block transfers between the input/output ("I/O") pins of the destination device and the memory devices of system 100. System 100 also includes design requirements that constrain the length of the transmission bus, the pitch between the bus lines, and the capacitive loading on the bus lines. Using these design requirements system 100 operates at a higher frequency than conventional memory systems. Accordingly, by increasing operating frequency the performance of system 100 increases, thus reducing the idle time of the destination device coupled to system 100.
Although a high operating frequency increases the data throughput of system 100, operating system 100 at a high frequency typically results in higher power dissipation and higher system temperature. In particular, memory devices are designed to follow a set of design specifications. Typically the specifications require that the memory devices operate below a given junction temperature ("Tj.sub.,max "). Additionally, provided the memory devices include a dynamic cell design, the specification also includes a periodic refresh rate. The refresh rate ensures that the storage cells of the dynamic device are periodically recharged. Increasing the operating frequency of a memory system, however, results in the memory devices of the memory system generating high power levels. The high power levels translate to an increase in the operating temperature of the memory devices. If the operating temperature of a memory device surpasses Tj.sub.,max the memory device may fail, thus resulting in the failure of the memory system.
To ensure lower operating temperatures, prior art memory systems implemented conventional thermal management techniques. In particular, to reduce the operating temperature of a memory device, prior art memory systems typically used specific packaging designs and specified the location of memory devices in memory systems. Conventional thermal management techniques, however, create numerous disadvantages.
One disadvantage of applying conventional thermal management results from the packaging designs of memory devices. In particular, conventional packaging designs are not always effective for dissipating power generated by devices operating at frequencies in excess of 100 Mhz, thus resulting in greater thermal dissipation requirements than prior art memory systems. Accordingly, the application of traditional packaging designs to reduce thermal dissipation prove ineffective in the thermal regulation of system 100.
Another disadvantage of applying conventional thermal management techniques is that conventional techniques place a constraint on the design layout of memory systems. In particular, conventional thermal management techniques require large distances between components to reduce heat transfer. In system 100, however, the devices are located in close proximity to each other in order to increase data throughput. Accordingly, the application of conventional placement techniques to reduce thermal dissipation prove ineffective in the thermal regulation of system 100.